JMD Modules Pass JEDEC Reliability Qualification Testing
AprIL 14, 2008 - < BACK
Atlanta, GA, April 14, 2008 - Jacket Micro Devices Inc. (JMD) announced that laminate-based radio frequency system-in-package (RF SiP) products made with its patented Multi-Layer Organic (MLO) process have passed JEDEC reliability qualification testing. The MLO substrates, and modules assembled using them, are lead (Pb) free and RoHS-compliant.
WLAN front-end modules using HDI 6-layer MLO substrates and containing both GaAs and SiGe die, assembled with standard wire-bond assembly techniques, were subjected to JEDEC test methods common to the semiconductor industry. Under an LTPD 5% sampling plan (0 rejects allowed per 45 samples, per lot) there was no performance degradation or failures. Manufacturing test specifications were used as the pass/fail criteria for initial and final RF tests, as well as CSAM for evaluating delamination during exposure to moisture soak and solder reflow. Modules passed pre-conditioning to MSL-3 at 260°C per JEDEC J-STD-020C, unbiased HAST (JESD22-A118), 500 hours HTOL (JESD22-A108C), 500 temperature cycles (JESD22-A104C), 45 thermal shock cycles (JESD22-A106), and biased HAST (JESD22-A110). The MLO substrates were fabricated at Microcircuit Technology in Singapore.
“We are very pleased with the initial results of our reliability qualification program” said Rick Clancy, JMD’s Director of Operations. “The key materials selected for MLO have outstanding environmental characteristics, such as low moisture uptake and high transition temperatures, so we were expecting to see results as good as or better than standard laminate packages.” He added, “Reliability qualification for semiconductor products is a continuous process and we will be conducting additional tests to ensure that SiP products using MLO meet the stringent requirements of the consumer electronics industry.”
Moisture resistance testing (pre-conditioning) approximates the standard factory environment to which parts are exposed during PCB assembly so that they can be properly packaged, stored, and handled to avoid damage during assembly solder reflow attachment and repair operations. Passing MSL 3/260 ensures the parts can withstand floor life exposure of 168 hours (at 30°C and 60% RH) and three solder reflow cycles to 260°C max. Stress test environments (such as High Temperature Operating Life, Highly Accelerated Stress Testing, Temperature Cycling and Thermal Shock) are used to accelerate typical field failure mechanisms. Passing results demonstrate reliability through the product’s useful life. Ongoing stress monitoring ensures continued reliability throughout the manufacturing lifecycle of the product.
About JMD
JMD is the leading supplier of organic packages with embedded passive components. JMD’s patented Multi-Layer Organic (MLO) technology defines a revolutionary, system-in-package (SiP) approach to RF modules that surpass ceramic and conventional laminate packages. JMD provides custom RF SiP design services and rapid prototyping using its extensive RF component library. JMD’s customers can access the company’s qualified high volume supply chain for rapid ramp to production volumes. For more information, visit www.jacketmicro.com or call +1 (404) 961-7240.
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